Memory device technology that three-dimensionally arranges memory cells has been discussed in, for example, JP-A 2007-266143. The memory device technology includes making memory holes in a stacked body in which a conductive layer, which functions as a control gate, and an insulating layer are multiply stacked alternately. A charge storage layer is formed on the inner walls of the memory holes, and silicon is subsequently provided in the memory holes.
Further, JP-A 2007-266143 discusses a stairstep structure of the conductive layers as a structure to connect each of the multiple stacked conductive layers to an upper layer interconnection. In other words, the conductive layers of lower layers are longer. A contact hole is made in an inter-layer insulating layer covering the stairstep structure to reach each of the conductive layers in the stairstep configuration; and a contact electrode is filled into the contact hole.
The depths of the contact holes reaching the conductive layers in the stairstep configuration are different. In the case where such contact holes are etched collectively, the etching processing time of the shallower contact holes connected to the conductive layers of the upper levels is relatively long. Such conditions may undesirably cause shorts between different conductive layers when a contact hole on the upper level side extends through the conductive layer of the intended connection to reach another conductive layer therebelow.